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Low Energy and Super-Efficient AI Chips | NextBigFuture.com

By Brian Wang

Low Energy and Super-Efficient AI Chips | NextBigFuture.com

Taalas and Etched are two AI chip startups aiming to challenge Nvidia's dominance in the AI hardware market.

Etched is using ASIC chips. Taalas is using eASIC chips. They are both putting the logic into the hardware instead of using software on top of GPUs. There is the potential to get 100 to 1000 times more energy efficient than more generalized hardware where the software handles the AI.

Etched has Transformer specific Application-Specific Integrated Circuits - ASIC

A transformer ASIC is a specialized chip that directly integrates the transformer architecture into the hardware. An application-specific integrated circuit is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec.

A successful commercial application of gate array circuitry was found in the low-end 8-bit ZX81 and ZX Spectrum personal computers, introduced in 1981 and 1982. These were used by Sinclair Research (UK) essentially as a low-cost I/O solution aimed at handling the computer's graphics.

Customization occurred by varying a metal interconnect mask. Gate arrays had complexities of up to a few thousand gates; this is now called mid-scale integration. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies also include random-access memory (RAM) elements.

In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer.

By the late 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist. Standard-cell integrated circuits (ICs) are designed in the following conceptual stages referred to as electronics design flow, although these stages overlap significantly in practice.

Today, gate arrays are evolving into structured ASICs that consist of a large IP core like a CPU, digital signal processor units, peripherals, standard interfaces, integrated memories, SRAM, and a block of reconfigurable, uncommitted logic. This shift is largely because ASIC devices are capable of integrating large blocks of system functionality, and systems on a chip (SoCs) require glue logic, communications subsystems (such as networks on chip), peripherals, and other components rather than only functional units and basic interconnection.

Full-custom ASIC design defines all the photolithographic layers of the device. Full-custom design is used for both ASIC design and for standard product design.

Structured ASIC design (also referred to as "platform ASIC design") is a relatively new trend in the semiconductor industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time).

EAsic's Halfway Between FGPA and ASIC

Intel eAsic devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. These devices provide lower unit-cost and lower power compared to FPGAs and faster time to market and lower non-recurring engineering cost compared to standard-cell ASICs. The new Intel® eASIC™ N5X devices, formerly codenamed Diamond Mesa, add a hard processor system and secure device managers compatible with Intel® FPGAs to extend Intel's logic portfolio offerings.

Here's a comparison of their approaches and technologies

Specialization - Transformer Specific - AI Model Specific Custom chips

Taalas:

- Develops "direct-to-silicon" chips customized for specific AI models

- Aims to create chips for various deep learning models, including transformers, SSMs, diffusers, and MoEs

Etched:

- Focuses exclusively on transformer models

- Their Sohu chip is designed specifically for training, deploying, and optimizing transformer-based language models

Performance Claims

Taalas:

- Claims their chips are 1000x more efficient than software counterparts[1]

- States that a single chip can outperform a small GPU data center[1]

Etched:

- Claims Sohu is over 10x faster and more cost-efficient than Nvidia's next-gen GPUs

- States that one 8xSohu server equals 160 H100 GPUs in performance

Chip Technology

Taalas:

- Uses an automated flow to turn AI models directly into custom silicon

- Aims to "cast intelligence directly into silicon" rather than simulating it on general-purpose computers

Etched:

- Focuses on application-specific integrated circuits (ASICs) tailored for transformer models

- Utilizes TSMC's 4nm process for chip manufacturing, Partnered with TSMC

Chip Timelines

Taalas:

- Plans to tape out its first large language model chip in Q3 2024

- Targeting availability to early customers in Q1 2025

Etched:

- Has already developed its first product, the Sohu chip

- Launching the Sohu Developer Cloud platform for customer previews and customizations

Taalas:

- Founded by Ljubisa Bajic, Lejla Bajic, and Drago Ignjatovic, with experience from Tenstorrent

Etched:

- Founded by Harvard dropouts Gavin Uberti and Chris Zhu

While both companies are taking on the challenge of competing with Nvidia, they have different approaches to specialization and market focus. Taalas appears to be more flexible in targeting various AI models, while Etched is betting heavily on the continued dominance of transformer architectures in AI.

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